Dynamic surface codes open new avenues for quantum error correction

Quantum error correction on a hexagonal lattice

In our Willow architecture, each physical qubit is connected to its four nearest neighbors, forming a square lattice. This arrangement of connections allows gates between the neighboring qubits, but also introduces design constraints, such as the overhead of extra wires needed to control couplers between qubits. Realizing error correction instead on a hexagonal lattice would permit each qubit to connect with only three neighbors instead of four, thereby simplifying the design and fabrication process of these large chips and enhancing hardware performance.

To achieve error correction with only three couplers per qubit, we make use of dynamic circuits that feature two distinct types of error correction cycles. Both cycle types leverage three couplers per qubit, with one coupler utilized twice within the cycle. The result is a quantum error correction circuit with dynamic, overlapping detecting regions that can still be used to triangulate errors, but only requiring three couplers per qubit.

We evaluated this three-coupler error correction circuit on our Willow processor, which has square connectivity. To measure the hexagonal code, we turned off all the unused couplers, to simulate the performance of hexagonal connectivity. We found that as the code’s distance scales from 3 to 5, the logical error rate improves by a factor of 2.15, matching the performance of a traditional static circuit operating on the same hardware that we presented in our milestone experiment last year.

Our findings demonstrate the feasibility of constructing a hexagonal qubit lattice for quantum error correction, a design space we thoroughly investigated in simulation. By adopting a hexagonal lattice, we can significantly reduce the complexity of our optimization algorithms for selecting qubit and gate frequencies. This simplification leads to a 15% improvement in the simulated error suppression factor, showcasing the novel capabilities unlocked by designing a processor with three couplers per qubit, rather than four.